MIS transistors are usually used for conventional semiconductor nonvolatile memories. These memories use a phenomenon where the surface potential of a silicon substrate can be modified through an injection of charge from the silicon substrate into an insulating gate trap or a floating gate. Examples of these memories are an EPROM (ultra-violet ray erasing type nonvolatile memory) and an EEPROM (electrically rewritable nonvolatile memory).
These nonvolatile memories, however, have disadvantages in that the information re-writing voltage is usually high (about 20 V), and the re-writing time is extremely long (several tens of msec. for the EEPROM). In addition, the information re-writing number is very small, typically about 10,000, thus posing problems for repeated use.
With a nonvolatile memory using a ferroelectric material capable of an electrically inverting polarization, the writing-in and reading-out times are substantially the same in principle, and the polarization is maintained even if the power source is disconnected. Thus, the memory can possibly be an ideal nonvolatile memory. Proposals for such a nonvolatile memory using a ferroelectric material include structures having a ferroelectric capacitor integrated on a silicon substrate as shown in U.S. Pat. No. 4,149,302, and a ferroelectric film provided on a gate portion of a MIS transistor as shown in U.S. Pat. No. 3,832,700.
Further, a nonvolatile memory having a laminate structure of a MOS semiconductor device as shown in FIG. 3 has been recently proposed in the IEDM, '87 pp, 850-851. In FIG. 3, reference numeral 301 designates a P-type Si substrate, 302 designates a LOCOS oxide film for isolation, 303 designates an N-type diffusion layer constituting a source, 304 designates an N-type diffusion layer constituting a drain, 305 designates a gate electrode, and 306 designates an interlayer insulation film. Designated by reference numeral 309 is a ferroelectric film which forms a capacitor with upper and lower electrodes 310 and 311 having the ferroelectric film therebetween. Reference numeral 307 illustrates a second interlayer insulation film and 312 designates an Al lead, wiring or interconnection electrode which connects the upper electrode 310 to the source diffusion layer 303.
In such a ferroelectric memory structure, the upper electrode 310 is formed by using Pt and the like in view of its contact with the ferroelectric film 309. The wiring or interconnection is carried out by using the wiring electrode 312. With such a structure, the cell area is increased, and a high density integration is not attained. The present invention seeks to solve this problem, and its objective is to provide a ferroelectric memory which has a reduced memory cell area and is suitable for integration.